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Berkeley IRAM project
A 1996–2004 research project in the Computer Science Division of the University of California, Berkeley, the Berkeley IRAM project explored computer architecture enabled by the wide bandwidth between memory and processor made possible when both are designed on the same integrated circuit (chip).〔(Project history. ) Retrieved 2011-03-30.〕 Since it was envisioned that such a chip would consist primarily of random-access memory (RAM), with a smaller part needed for the central processing unit (CPU), the research team used the term "Intelligent RAM" (or IRAM) to describe a chip with this architecture.〔Patterson, et al. (1997) ''IEEE Micro,'' 17 (2), p. 34.〕 Like the J–Machine project at MIT, the primary objective of the research was to avoid the Von Neumann bottleneck which occurs when the connection between memory and CPU is a relatively narrow memory bus between separate integrated circuits.
==Theory==
(詳細はstatic random-access memory (SRAM), which may be implemented using circuit technology optimized for logic performance, rather than the denser and lower-cost dynamic random-access memory (DRAM), which is not. Microprocessor access to off-chip memory costs time and power, however, significantly limiting processor performance. For this reason computer architecture employing a hierarchy of memory systems has developed, in which static memory is integrated with the microprocessor for temporary, easily accessible storage (or cache) of data which is also retained off-chip in DRAM.〔Hennesey & Patterson (2007) Ch. 5〕 Since the on-chip cache memory is redundant, its presence adds to cost and power. The purpose of the IRAM research project was to find if (in some computing applications) a better trade-off between cost and performance could be achieved with an architecture in which DRAM was integrated on-chip with the processor, thus eliminating the need for a redundant static memory cache—even though the technology used was not optimum for DRAM implementation.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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